In the fabrication of semiconductor circuits, the nature and type of the processing steps significantly affect the electrical circuit performance of the completed devices. This is particularly true when bipolar transistors are utilized in MTL (I.sup.2 L) circuits, where it is desirable to minimize the area of each region where minority carriers (i.e., electrons in a P type semiconductor region and holes in N type semiconductor regions) may be stored.
Generally, it is desirable to provide enhanced circuit performance by reducing the distance between the base and collector contacts of the transistors, and by reducing the base-emitter depletion layer capacitance, stored charge, and the base series resistance.
While it is generally known that these electrical characteristics should be enhanced to provide improved circuit performance, fabrication of a circuit to achieve these is not always simple, particularly if considerations must be taken of the design layout, density, and wirability of the circuit. Additionally, while techniques such as self-alignment are generally known for reducing the number of masking steps required, the provision of a process which achieves all of these desired characteristics has not heretofore been presented.
The circuit parameters to be considered in the design of MTL/I.sup.2 L circuits have been identified and discussed in an article by Berger and Helwig which appeared in the IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, April, 1979, at page 327. While those authors have pointed out the parameters which determine the speed limit of MTL circuits using bipolar transistors, a method for fabricating such a circuit and the circuit layout structure has have not been provided. They do, however, mention the use of oxide collars and the use of polysilicon as a low-ohmic bypass for the base current.
Another reference of interest is copending application Ser. No. 912,919, filed June 6, 1978, and assigned to the present assignee. In that copending application, a process is described for forming NPN transistors where the emitters are self-aligned to the polysilicon base contacts. However, the process steps and the resultant structure are distinct from the present process and structure.
In view of the importance of MTL structures using bipolar devices, it is a primary object of the present invention to provide MTL circuits in which the collector regions/contacts and the base regions/contacts are mutually self-aligned.
It is another object of the present invention to provide a process for fabricating such MTL circuits including the step of mutually self-aligning the collectors and the base contacts.
It is another object of the present invention to provide MTL circuits having improved performance, power-delay product and wirability.
It is another object of the present invention to provide improved MTL circuit structures having increased device density and wherein self-alignment is achieved.
It is another object of the present invention to provide MTL circuits in which the collectors are self-aligned to polycrystalline semiconductor base contacts, and wherein a polycrystalline semiconductor layer or a layer of metal can be used to contact the collectors.
It is another object of the present invention to provide MTL circuits in which the base contacts are self-aligned to polycrystalline semiconductor collector contacts, and wherein a layer of metal or a polycrystalline semiconductor layer can be used for the base contacts.
It is another object of the present invention to provide semiconductor circuitry including bipolar transistors in which mutual self-alignment of the collector and base contacts is utilized to reduce the distance between the base and collector contacts, and in which the base series resistance is minimized by the provision of alternate base current paths.
It is another object of the present invention to provide semiconductor circuitry using bipolar transistors, where the circuit fabrication provides increased density and improved electrical performance, while at the same time enhancing wirability of the circuits.
It is another object of the present invention to provide a technique for fabricating MTL circuits in which the collectors are self-aligned to the polycrystalline semiconductor base contacts, and wherein a polycrystalline semiconductor layer or a layer of metal or refractory metal-silicide can be used for the collector contacts.
It is another object of the present invention to provide a technique for fabricating MTL circuits in which the base contacts are self-aligned to the polycrystalline semiconductor collector contacts, and wherein a polycrystalline semiconductor layer or a layer of metal or refractory metal-silicide can be used for the base contacts.